ASME's Mechanical Engine…ing Toolkit 1997 December/ASME's Mechanical Engineering Toolkit 1997 December.iso/intel/8259.lzh/8259.TXT

Text File | 1986-01-26 | 6KB | 125 lines

                 The 8259 Interrupt Controller

   The 8259 Interrupt Controller chip provides a vital support service for the
central processor (8088). We have already seen how external events can be
signaled to the central processor via its interrupt mechansim. In a typical
Personal Computer system, such interrupt signals can originate from several
different places (i.e. keyboard,disk drive,etc.). The 8088, however,
has only one input line on which to receive an interrupt signal. The 8259
chip is therefore employed to manage the various interrupt sources and
present a single, controllable interrupt signal to the central processor.

   As configured for use in the PC, the 8259 chip can accept up to eight
independent signals, numbered 0 through 7. For each interrupt
it receives, the 8259 can present an interrupt signal to the 8088. Furthermore
it presents to the 8088 a unique interrupt type code for each of the
eight interrupt sources. This allows us to assign a unique interrupt-service
routine to each different interrupt source. The eight signal inputs to the
8259 are wired onto the control bus so that any device tied into the bus
system can access this interrupt mechansim. On the control bus, the signals
are named IRQ0 through IRQ7.

   Because each signal is independent, provision must be made for the pos-
siblity of two or more signals occurring at the same time. The 8259 manages
such an event by holding on to the secondary interrupt(s) while the
processor services the first. When that interrupt has been serviced, the
next one is signaled to the processor. For events that occur at exactly the
same moment, the 8259 passes them to the processor in a priority order,
where interrupt source 0 has the highest priority and interrupt source 7
has the lowest. One very important consequence of this scheme is that the
processor (8088) must indicate to the controller (8259) when it has com-
pleted the servicing of each interrupt. This must be kept in mind whenever
an interrupt-service routine is written.

   Because it has been designed for use in many different applications, the
8259 is an extremely complex chip. Fortunately for us, however, most of
this complexity is handled by the BIOS, which programs the proper config-
uration information into the 8259 on power-up. The 8259 is thus configured
to signal interrupt type codes 08H-0FH to correspond with interrupt
sources 0-7. The standard device allocations for each of these
interrupt sources are listed in Table 5-3. Note that the two highest-priority
interrupts, IRQ0 and IRQ1, are wired directly on the system board. The
rest of the interrupt sources are obtained from adapter cards plugged into
the expansion slots.

   From our point of view, programming the 8259 consists of two basic
actions. See Fig. 5-3. First, we can enable or disable each interrupt source
independently by writing a value into the interrupt mask register, or IMR.
The IMR is a one-byte register within the 8259 that we can access via I/O
port 21H. Each bit in the IMR corresponds to the interrupt source with its
bit number (i.e. bit 0-IRQ0,bit 1-IRQ1,etc). If a bit in the IMR is 0, then
its corresponding interrupt source in enabled. A signal appearing on that
input to the 8259 will cause an interrupt to be sent to the 8088. If the IMR
bit is 1, then the interrupt source is disabled (or masked) and cannot gen-
erate an interrupt. For example, suppose we wish to disable interrupts
from all devices except the keyboard. This would be accomplished as follows:
        MOV    AL,0FDH
        OUT    21H,AL
Keep in mind that the state of the interrupt flag within the 8088 will
ultimately determine whether or not any interrupt signal is received.

   The second 8259 programming action that we must be concerned with is
the signaling of the end of an interrupt service routine. This is
accomplished by sending the "end of interrupt" (EOI) command, represented by
20H, to the interrupt command register within the 8259. Coincidentally,
this one-byte register is accessed via I/O port 20H. That is all there is to
controlling the interrupt mechanism.


               Table 5-3. Interrupt Sources

   8259 Input          Type Code                        Device

     IRQ0                 08H                       Timer (Channel 0)
     IRQ1                 09H                Keyboard
     IRQ2                 0AH                       Color Graphics Interface
     IRQ3                 0BH                       Unused
     IRQ4                 0CH                       Serial (RS-232) Interface
     IRQ5                 0DH                       Unused
     IRQ6                 0EH                       Diskette
     IRQ7                 0FH                       Printer




             Fig. 5-3. Controlling the Interrupt Mechanism

        IF        Interrupt Flag, within 8088
            IF=0: All interrupts disabled (use cli instruction).
            IF=1: Interrupts enabled (use sti instruction).

    7  6  5  4  3  2  1  0          Interrupt Mask Register
        |  |  |  |  |  |  |  |           IMR Bit=0: IRQ enabled
        |  |  |  |  |  |  |  IRQ0     IMR Bit=1: IRQ disabled
        |  |  |  |  |  |  IRQ1        Set IMR with MOV  AL,xyz
        |  |  |  |  |  IRQ2                        OUT  21H,AL
        |  |  |  |  IRQ3
        |  |  |  IRQ4
        |  |  IRQ5
        |  IRQ6
        IRQ7


                      Interrupt Command Register
                      Signal end of interrupt by sending
                      EOI command: MOV AL,20H
                           OUT 20H,AL